Good news…Bad news…

(Geeky post for friends who are on the same frequency...)

After camping in the EE lab and 24hr cluster for the past few days, we FINALLY figured out how to play around the signals, synchronized the baud rate of the FPGA and the Terminal, and managed get some output from the RS232 of the FPGA board!!! (Yeahhh!!!!! *Jump around and scream*)

However, the output is not really what we wanted...Sigh...

We are sending out integers from the board and are expecting integers as the output on the Terminal. However, the output we are getting is either in ASCII character or hexadecimal format. As far as I know, these formats are not supported by Matlab and hence, the processed image can’t be recomposed. Dammit!!!

Also, we just realize another problem in the whole output-data issue. While our algorithm is churning out one integer per clock cycle, the RS232 will take a few clock cycles (1 start bit, 8 data bit, 1 stop bit ) to output one just integer.

3 more days to presentation...

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When things seem hopeless, that's when we should be most excited...
Cos that's when there's so much room for us to make a difference...